1. Technical Field
The present invention relates to configuration memory cells used in a Programmable Logic Device (PLD). More particularly, the present invention relates to programming of high density configuration memory cells to increase soft error immunity when SINGLE EVENT UPSETs (SEUs) can occur.
2. Related Art
Traditional PLDs such as Complex PLDs (CPLDs) and Field Programmable Gate Arrays (FPGAs) typically use millions of Static Random Access Memory (SRAM) configuration memory cells to program the functionality of the implemented circuit. The presence of an increasing number of SRAM configuration memory cells in a PLD, with chip geometries becoming smaller and supply voltages becoming lower, increases the likelihood that the configuration memory cell storage state will become upset due to collisions with cosmic particles, or single event upsets (SEUs). With SEUs more likely to occur, the mean time to failure for a particular program configuration for the PLD will increase.
For reference, a block diagram of components of one PLD, a conventional FPGA, is shown in FIG. 1. The FPGA includes input/output (IOBs) blocks 2 (each labeled 10) located around the perimeter of the FPGA, multi-gigabit transceivers (MGT) 4 interspersed with the I/O blocks 2, configurable logic blocks 6 (each labeled CLB) arranged in an array, block random access memory 8 (each labeled BRAM) interspersed with the CLBs, configuration logic 12, a configuration interface 14, an on-chip processor 16, and an internal configuration access port (ICAP) 15. The FPGA also includes a programmable interconnect structure (not shown) made up of traces that are programmably connectable between the CLBs 6 and IOBs 2 and BRAMs 8.
The configuration memory array 17 typically includes millions of the SRAM memory cells shown in FIG. 1. The SRAM cells are programmed to configure the CLBs 6, IOBs 2, BRAMs 8 and appropriately connect the interconnect lines. Configuration data is provided to the SRAM cells of the configuration memory array 17 as a bitstream from an external memory (e.g., an external PROM) via configuration interface 14 and configuration logic 12. The configuration logic 12 provides for programming of the SRAM configuration memory array cells 17 at startup. The FPGA can be reconfigured by rewriting data in the configuration memory array cells 17 using the ICAP 15 or the conventional configuration interface.
FIG. 2 illustrates the second type PLD, a CPLD, further illustrating the use of a configuration memory array in a PLD. CPLDs have a similar structure to FPGAs with IOBs 20 at the chip periphery, and a large SRAM configuration memory array 22 lying beneath the logic circuitry. Instead of CLBs of an FPGA, the CPLD logic includes a number of logic blocks (LBs) 24, each containing a number of wide AND gates that have outputs connected to one or more wide OR gates. A switch matrix 26 made up of interconnect lines 27 with programmable interconnect points PIPs 28 is used to programmably interconnect the IOBs 20 and LBs 24. The large SRAM configuration memory 22 made of millions of SRAM memory cells allows for programming of the PIPs 28, as well as components of the IOBs 20 and LBs 24. The configuration memory array 22 is programmed using programming or configuration logic 30 using data obtained through the configuration interface 32.
FIG. 3 shows the prior art PLD, which includes SRAM configuration memory cells 40 and logic 41. The logic 41 may be either the CLBs for an FPGA as shown in FIG. 3. The SRAM configuration memory cells 40 can also be connected to PIPs or other logic, such as in an 10B. The SRAM configuration memory cells 40 are written by the configuration logic 42, which reads the data from a PROM 44 through a configuration interface 43, the PROM typically residing off the chip. The SRAM configuration memory cells 40 are typically programmed just once upon power up, but can be reconfigured frame by frame during operation.
One solution to reducing the total chip area required for configuration memory cells is to use Dynamic Random Access Memory (DRAM) cells. This solution is described in U.S. Pat. No. 5,847,577 entitled, “DRAM Memory Cell For Programmable Logic Devices” by Stephen Trimberger, which is incorporated by reference herein in its entirety. The two most common types of memory cells are SRAM and DRAM. The main advantage of DRAM is high density, while the advantage of SRAM cells is fast access time. A DRAM memory cell includes less circuitry, resulting in a higher cell density, but will not maintain a memory state indefinitely and will include refresh circuitry to periodically reprogram the DRAM memory cells. Lower density SRAMs when compressed into higher densities to occupy the same area as a DRAM cell will experience more errors due to SEUs than the comparable DRAM cell. Whether DRAM or SRAM cells are used for the configuration memory, SEUs can still affect the state of the configuration memory, causing a decrease in the soft error immunity.
It would be desirable to provide configuration memory cells in a PLD with components programmed or configured to deal with SEUs to maintain soft error immunity. It is further desirable to provide programming adaptability so that soft error immunity can be maintained irrespective of the density of configuration cells, and whether DRAM or SRAM cells are used in the configuration memory.